drm/i915/skl: Determine SKL slice/subslice/EU info
authorJeff McGee <jeff.mcgee@intel.com>
Fri, 13 Feb 2015 16:27:54 +0000 (10:27 -0600)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Mon, 23 Feb 2015 22:56:59 +0000 (23:56 +0100)
commit3873218f359a411bf98f6d1d6d15a44f64933163
tree65758a3340f705aa9bf1386a44ab6bc2c5bcf2cd
parentd0bbbc4faf7bc1225ffd5d159fbe2c8dfef75333
drm/i915/skl: Determine SKL slice/subslice/EU info

Read fuse registers to determine the available slice total,
subslice total, subslice per slice, EU total, and EU per subslice
counts of the SKL device. The EU per subslice attribute is more
precisely defined as the maximum EU available on any one subslice,
since available EU counts may vary across subslices due to fusing.
Set flags indicating the SKL device's slice/subslice/EU (SSEU)
power gating capability. Make all values available via debugfs
entry 'i915_sseu_status'.

v2: Several small clean-ups suggested by Damien. Most notably,
    used smaller types for the new device info fields to reduce
    memory usage and improved the clarity/readability of the
    method used to extract attribute values from the fuse
    registers.

Signed-off-by: Jeff McGee <jeff.mcgee@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_debugfs.c
drivers/gpu/drm/i915/i915_dma.c
drivers/gpu/drm/i915/i915_drv.h
drivers/gpu/drm/i915/i915_reg.h