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ASoC: Fix WM8996 24.576MHz clock operation
authorMark Brown <broonie@opensource.wolfsonmicro.com>
Sat, 10 Dec 2011 12:38:32 +0000 (20:38 +0800)
committerMark Brown <broonie@opensource.wolfsonmicro.com>
Sat, 10 Dec 2011 19:01:09 +0000 (03:01 +0800)
commit37d5993c5cc9bc83762ae1b5bd287438022e8afe
tree9d05123c5b167ab8bb3b815e5becf537d54bfd92tree | snapshot (tar.gz zip)
parent974edd30beafdb136cdfc6839a143e23c826dc89commit | diff
ASoC: Fix WM8996 24.576MHz clock operation

Record the clock after the divider as that is what all SYSCLK users see.
Without this the other clock configuration in the device comes out at
half rate.

Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Cc: stable@kernel.org
sound/soc/codecs/wm8996.c diff | blob | blame | history