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drm/amd/powerplay: fix vce cg logic error on CZ/St.
authorRex Zhu <Rex.Zhu@amd.com>
Tue, 10 Jan 2017 11:26:49 +0000 (19:26 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 12 Jan 2017 22:39:11 +0000 (17:39 -0500)
commit3731d12dce83d47b357753ffc450ce03f1b49688
treee873e0ff705c220f99c8c1959ca5805ab9042dc6tree | snapshot (tar.gz zip)
parenta628392cf03e0eef21b345afbb192cbade041741commit | diff
drm/amd/powerplay: fix vce cg logic error on CZ/St.

can fix Bug 191281: vce ib test failed.

when vce idle, set vce clock gate, so the clock
in vce domain will be disabled.
when need to encode, disable vce clock gate,
enable the clocks to vce engine.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/powerplay/hwmgr/cz_clockpowergating.c diff | blob | blame | history