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(parent: 48e5d68) | patch
drm/i915: Clean up L3 SQC register field definitions
authorImre Deak <imre.deak@intel.com>
Tue, 3 May 2016 12:54:20 +0000 (15:54 +0300)
committerImre Deak <imre.deak@intel.com>
Tue, 3 May 2016 13:49:15 +0000 (16:49 +0300)
commit36579cb63b87b7a4406b9b19c8ff376ca701083b
tree08a5555290f7b17085f9d3ae959197b642208e13tree | snapshot (tar.gz zip)
parent48e5d68d28f00c0cadac5a830980ff3222781abbcommit | diff
drm/i915: Clean up L3 SQC register field definitions

No need for hard-coding the register value, the corresponding fields are
defined properly in BSpec.

No functional change.

v2:
- Rebased on BXT L3 SQC tuning patch merged meanwhile.

CC: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> (v1)
Link: http://patchwork.freedesktop.org/patch/msgid/1462280061-1457-3-git-send-email-imre.deak@intel.com
drivers/gpu/drm/i915/i915_reg.h diff | blob | blame | history
drivers/gpu/drm/i915/intel_pm.c diff | blob | blame | history
drivers/gpu/drm/i915/intel_ringbuffer.c diff | blob | blame | history