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(parent: 02a5417) | patch
MIPS: R5000: Fix TLB hazard handling.
authorRalf Baechle <ralf@linux-mips.org>
Tue, 16 Oct 2012 20:13:06 +0000 (22:13 +0200)
committerRalf Baechle <ralf@linux-mips.org>
Tue, 16 Oct 2012 20:22:23 +0000 (22:22 +0200)
commit359187d647a7a7813444ff5932d0b862f970bb0f
tree1516d43b7b33e03f8b531552764a3e8406dde8bftree | snapshot (tar.gz zip)
parent02a5417751c31cd64197652c000a5ab0d3261465commit | diff
MIPS: R5000: Fix TLB hazard handling.

R5000 and the Nevada CPUs (RM5230, RM5231, RM5260, RM5261, RM5270 and
RM5271) are basically the same CPU core and all are documented to require
two instructions separating a write to c0_pagemask, c0_entryhi, c0_entrylo0,
c0_entrylo1 or c0_index.

So far we were only providing on cycle before / after a TLBR/TLBWI
for R5000 but 3 cycles before and 1 cycles after for the Nevadas.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/mm/tlbex.c diff | blob | blame | history