x86: Eliminate redundant/contradicting cache line size config options
authorJan Beulich <JBeulich@novell.com>
Fri, 13 Nov 2009 11:54:40 +0000 (11:54 +0000)
committerIngo Molnar <mingo@elte.hu>
Thu, 19 Nov 2009 03:58:34 +0000 (04:58 +0100)
commit350f8f5631922c7848ec4b530c111cb8c2ff7caa
treed81bd9432ac1f130779fa7272322681169184867
parent508d85c2c6bc8cba53d2a54d9a306ad64a0a80bf
x86: Eliminate redundant/contradicting cache line size config options

Rather than having X86_L1_CACHE_BYTES and X86_L1_CACHE_SHIFT
(with inconsistent defaults), just having the latter suffices as
the former can be easily calculated from it.

To be consistent, also change X86_INTERNODE_CACHE_BYTES to
X86_INTERNODE_CACHE_SHIFT, and set it to 7 (128 bytes) for NUMA
to account for last level cache line size (which here matters
more than L1 cache line size).

Finally, make sure the default value for X86_L1_CACHE_SHIFT,
when X86_GENERIC is selected, is being seen before that for the
individual CPU model options (other than on x86-64, where
GENERIC_CPU is part of the choice construct, X86_GENERIC is a
separate option on ix86).

Signed-off-by: Jan Beulich <jbeulich@novell.com>
Acked-by: Ravikiran Thirumalai <kiran@scalex86.org>
Acked-by: Nick Piggin <npiggin@suse.de>
LKML-Reference: <4AFD5710020000780001F8F0@vpn.id2.novell.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
arch/x86/Kconfig.cpu
arch/x86/boot/compressed/vmlinux.lds.S
arch/x86/include/asm/cache.h
arch/x86/kernel/vmlinux.lds.S
arch/x86/mm/tlb.c