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(parent: 0f350f0) | patch
clk: socfpga: Add a second parent option for the dbg_base_clk
authorDinh Nguyen <dinguyen@opensource.altera.com>
Sat, 25 Jul 2015 03:30:18 +0000 (22:30 -0500)
committerMichael Turquette <mturquette@baylibre.com>
Mon, 24 Aug 2015 23:49:03 +0000 (16:49 -0700)
commit34d5003bfba44a73fe9fbcf75e1d41d130d59bd1
tree6cb63c13a13c1f257a6c15991cf00dd009864517tree | snapshot (tar.gz zip)
parent0f350f063eb62212a701a512f74e63ae4714441ccommit | diff
clk: socfpga: Add a second parent option for the dbg_base_clk

The debug base clock can be bypassed from the main PLL to the OSC1 clock.
The bypass register is the staysoc1(0x10) register that is in the clock
manager.

This patch adds the option to get the correct parent for the debug base
clock.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
drivers/clk/socfpga/clk-periph.c diff | blob | blame | history
drivers/clk/socfpga/clk.h diff | blob | blame | history