drm/msm/dsi: Save/Restore PLL status across PHY reset
authorHai Li <hali@codeaurora.org>
Fri, 3 Jul 2015 14:09:46 +0000 (10:09 -0400)
committerRob Clark <robdclark@gmail.com>
Sat, 15 Aug 2015 22:27:18 +0000 (18:27 -0400)
commit328e1a633c9bc26c36ecd320246e4a9b2726e81a
tree662e05c96fd1cf2bf0d6e059a32479d374616ac3
parentda882cd1ee132ecbb4a4848a6b0797ea2ed4bee7
drm/msm/dsi: Save/Restore PLL status across PHY reset

Reset DSI PHY silently changes its PLL registers to reset status,
which will make cached status in clock driver invalid and result
in wrong output rate of link clocks. The current restore mechanism
in DSI PLL does not cover all the cases. This change is to recover
PLL status after PHY reset to match HW status with cached status
in clock driver.

Signed-off-by: Hai Li <hali@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
drivers/gpu/drm/msm/dsi/dsi.h
drivers/gpu/drm/msm/dsi/dsi_manager.c
drivers/gpu/drm/msm/dsi/pll/dsi_pll.c
drivers/gpu/drm/msm/dsi/pll/dsi_pll.h
drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c