drm/i915/skl: Register definitions for SKL Clocks
authorSatheeshakrishna M <satheeshakrishna.m@intel.com>
Thu, 13 Nov 2014 14:55:13 +0000 (14:55 +0000)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Fri, 14 Nov 2014 10:17:51 +0000 (11:17 +0100)
commit326ac39b68e6aeb57d81c60c6078989955c225b5
tree0610ce4eee6590764e5441433398e8a738d5e5df
parent92122789b2d699a1e82dca502940e0dd37bf6f3b
drm/i915/skl: Register definitions for SKL Clocks

This patch defines the necessary SKL registers for implementing the
new clocking mechanism.

v2: Addressed review comments by Damien
- Added code comment
- Introduced enum for WRPLL values

v3: Rebase on top of nightly (minor conflict in i915_reg.h)

v4: Use 0x, not 0X (Ville)

v5: Modified as per review comments from Paulo

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Satheeshakrishna M <satheeshakrishna.m@intel.com> (v2)
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> (v3,v4)
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_reg.h