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drm/i915: IVB FBC WaFbcAsynchFlipDisableFbcQueue
authorRodrigo Vivi <rodrigo.vivi@gmail.com>
Mon, 6 May 2013 22:37:34 +0000 (19:37 -0300)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Fri, 10 May 2013 19:56:48 +0000 (21:56 +0200)
commit30ca7c6f97e266d122b03261f75f530d5c83608b
tree6f830937df98ce1d9e6c15c96f2f2b94a411ca37tree | snapshot (tar.gz zip)
parentabe959c7e06f62f064432a2aa00c199f1f672c81commit | diff
drm/i915: IVB FBC WaFbcAsynchFlipDisableFbcQueue

Display register 42000h bit 22 must be set to 1b for the entire time that
Frame Buffer Compression is enabled.

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_pm.c diff | blob | blame | history