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(parent: f014a55) | patch
[PATCH] x86: when L3 is present show its size in /proc/cpuinfo
authorVenkatesh Pallipadi <venkatesh.pallipadi@intel.com>
Sun, 30 Oct 2005 22:59:38 +0000 (14:59 -0800)
committerLinus Torvalds <torvalds@g5.osdl.org>
Mon, 31 Oct 2005 01:37:12 +0000 (17:37 -0800)
commit30037f66ce63b6b7ca1fbfb06605b831f4a60df6
tree48645e204613332df510b42f56655d06d9200a33tree | snapshot (tar.gz zip)
parentf014a556e714dfb02502e3be6146a39ca625f33ccommit | diff
[PATCH] x86: when L3 is present show its size in /proc/cpuinfo

The code that prints the cache size assumes that L3 always lives in chipset
and is shared across CPUs.  Which is not really true.

I think all the cachesizes reported by cpuid are in the processor itself.
The attached patch changes the code to reflect that.

Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
arch/i386/kernel/cpu/intel_cacheinfo.c diff | blob | blame | history
Motorola kernel-slsi