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MIPS: OCTEON: Use correct instruction to read 64-bit COP0 register
authorChandrakala Chavva <cchavva@caviumnetworks.com>
Thu, 15 Jan 2015 13:11:08 +0000 (16:11 +0300)
committerRalf Baechle <ralf@linux-mips.org>
Fri, 20 Feb 2015 14:29:36 +0000 (15:29 +0100)
commit2d98cae6e35cfda8c008dba9c43c6f78f85e2792
tree6e70675d29a49b129722a426b7fad04d05a0213ctree | snapshot (tar.gz zip)
parent6b3a287e6351b00df6624b41c160e1c0817f40e2commit | diff
MIPS: OCTEON: Use correct instruction to read 64-bit COP0 register

Use dmfc0/dmtc0 instructions for reading CvmMemCtl COP0 register,
its a 64-bit wide.

Signed-off-by: Chandrakala Chavva <cchavva@caviumnetworks.com>
Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: David Daney <david.daney@cavium.com>
Patchwork: https://patchwork.linux-mips.org/patch/8936/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/kernel/octeon_switch.S diff | blob | blame | history
Motorola kernel-slsi