drm/i915: Use the memory latency based WM computation on VLV too
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Wed, 24 Jun 2015 19:00:06 +0000 (22:00 +0300)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Mon, 29 Jun 2015 08:56:03 +0000 (10:56 +0200)
commit26e1fe4fbd4c15919f8cfa9440d70eca5a457ba3
tree7585af5e0101c098021354980dc893b0c7dd8232
parent54f1b6e15db87722aa21035169ce811af9d971fd
drm/i915: Use the memory latency based WM computation on VLV too

In order to get decnet memory self refresh residency on VLV, flip it
over to the new CHV way of doing things. VLV doesn't do PM5 or DDR DVFS
so it's a bit simpler.

I'm not sure the currently memory latency used for CHV is really
appropriate for VLV. Some further testing will probably be needed to
figure that out.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_display.c
drivers/gpu/drm/i915/intel_pm.c
drivers/gpu/drm/i915/intel_sprite.c