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(parent: 9387bfd) | patch
clk: rockchip: allow varying mux parameters for cpuclk pll-sources
authorXing Zheng <zhengxing@rock-chips.com>
Wed, 9 Mar 2016 02:37:03 +0000 (10:37 +0800)
committerHeiko Stuebner <heiko@sntech.de>
Sun, 27 Mar 2016 11:03:33 +0000 (13:03 +0200)
commit268aebaa2410152bf91ea1ede6b284ff8138822d
treef3831b0a1978eb3eeb0abf22d90e6c839a66f6f0tree | snapshot (tar.gz zip)
parent9387bfd19b457085189d918ef117ffd63c4d67a0commit | diff
clk: rockchip: allow varying mux parameters for cpuclk pll-sources

Thers are only two parent PLLs that APLL and GPLL for core on the
previous SoCs (RK3066/RK3188/RK3288/RK3368). Hence, we set fixed
GPLL as alternate parent when core is switching freq.

Since RK3399 big.LITTLE architecture, we need to select and adapt
more PLLs (ALPLL/ABPLL/DPLL/GPLL) sources.

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
drivers/clk/rockchip/clk-cpu.c diff | blob | blame | history
drivers/clk/rockchip/clk-rk3036.c diff | blob | blame | history
drivers/clk/rockchip/clk-rk3188.c diff | blob | blame | history
drivers/clk/rockchip/clk-rk3228.c diff | blob | blame | history
drivers/clk/rockchip/clk-rk3288.c diff | blob | blame | history
drivers/clk/rockchip/clk-rk3368.c diff | blob | blame | history
drivers/clk/rockchip/clk.h diff | blob | blame | history