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(parent: 77bbd89) | patch
drm/exynos: dsi: rename pll_clk to sclk_clk
authorHyungwon Hwang <human.hwang@samsung.com>
Fri, 12 Jun 2015 12:59:03 +0000 (21:59 +0900)
committerInki Dae <inki.dae@samsung.com>
Mon, 22 Jun 2015 11:05:00 +0000 (20:05 +0900)
commit26269af95af83145a3bccca41344c66502fdded9
tree10d7d375f751e2a61cc1a9c0a51c4d6c07cb7ee0tree | snapshot (tar.gz zip)
parent77bbd8914a91fab25f567772db60e2d1372de8c6commit | diff
drm/exynos: dsi: rename pll_clk to sclk_clk

This patch renames pll_clk to sclk_clk. The clock referenced by pll_clk
is actually not the pll input clock for dsi. The pll input clock comes
from the board's oscillator directly. But for the backward
compatibility, the old clock name "pll_clk" is also OK.

Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Documentation/devicetree/bindings/video/exynos_dsim.txt diff | blob | blame | history
drivers/gpu/drm/exynos/exynos_drm_dsi.c diff | blob | blame | history