crypto: caam - handle core endianness != caam endianness
authorHoria Geantă <horia.geanta@nxp.com>
Thu, 19 May 2016 15:11:26 +0000 (18:11 +0300)
committerHerbert Xu <herbert@gondor.apana.org.au>
Tue, 31 May 2016 08:41:54 +0000 (16:41 +0800)
commit261ea058f016bc04fa064348ad9bf39d94379381
treef79333970109faac5f03b2f7c181f3c8f36effea
parentbd52f1c23255a7c355268215c3c75aabbe11a67a
crypto: caam - handle core endianness != caam endianness

There are SoCs like LS1043A where CAAM endianness (BE) does not match
the default endianness of the core (LE).
Moreover, there are requirements for the driver to handle cases like
CPU_BIG_ENDIAN=y on ARM-based SoCs.
This requires for a complete rewrite of the I/O accessors.

PPC-specific accessors - {in,out}_{le,be}XX - are replaced with
generic ones - io{read,write}[be]XX.

Endianness is detected dynamically (at runtime) to allow for
multiplatform kernels, for e.g. running the same kernel image
on LS1043A (BE CAAM) and LS2080A (LE CAAM) armv8-based SoCs.

While here: debugfs entries need to take into consideration the
endianness of the core when displaying data. Add the necessary
glue code so the entries remain the same, but they are properly
read, regardless of the core and/or SEC endianness.

Note: pdb.h fixes only what is currently being used (IPsec).

Reviewed-by: Tudor Ambarus <tudor-dan.ambarus@nxp.com>
Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
drivers/crypto/caam/Kconfig
drivers/crypto/caam/caamhash.c
drivers/crypto/caam/ctrl.c
drivers/crypto/caam/desc.h
drivers/crypto/caam/desc_constr.h
drivers/crypto/caam/jr.c
drivers/crypto/caam/pdb.h
drivers/crypto/caam/regs.h
drivers/crypto/caam/sg_sw_sec4.h