ARM: dts: dra7: Fix up unaligned access setting for PCIe EP
authorVignesh R <vigneshr@ti.com>
Tue, 25 Sep 2018 05:21:51 +0000 (10:51 +0530)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Tue, 13 Nov 2018 19:15:07 +0000 (11:15 -0800)
commit255fb2e03694901f8178d9766ab3c043be6ed33b
tree01493c09d38974ddb16638ffea401973ab326269
parent074df512d4d02eaf793ffddf46ab45cdaba374e1
ARM: dts: dra7: Fix up unaligned access setting for PCIe EP

commit 6d0af44a82be87c13f2320821e9fbb8b8cf5a56f upstream.

Bit positions of PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE and
PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE in CTRL_CORE_SMA_SW_7 are
incorrectly documented in the TRM. In fact, the bit positions are
swapped. Update the DT bindings for PCIe EP to reflect the same.

Fixes: d23f3839fe97 ("ARM: dts: DRA7: Add pcie1 dt node for EP mode")
Cc: stable@vger.kernel.org
Signed-off-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
arch/arm/boot/dts/dra7.dtsi