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author	Zhenyu Wang <zhenyuw@linux.intel.com>
	Thu, 23 Jul 2009 17:00:29 +0000 (01:00 +0800)
committer	Eric Anholt <eric@anholt.net>
	Wed, 29 Jul 2009 22:16:01 +0000 (15:16 -0700)
commit	249c0e64c24bf455a4e4815f72750f2b16cedd94
tree	0a75d3f0f48acdd5341a9670dc7c860af7669940	tree \| snapshot (tar.gz zip)
parent	24f119c769bacac5729297b682fec7811a983cc6	commit \| diff

drm/i915: fix issue in display pipe setup on IGDNG

During pipe DPMS off, instead of busy waiting pipe off, insert
delays during wait and don't loop after enough tries which matches
spec requirement. Also try to match DPMS on path by disable FDI TX
PLL in DPMS off. Disable PF by writing PF_WIN_SZ which really trigger
the update.

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>

drivers/gpu/drm/i915/i915_reg.h		diff \| blob \| blame \| history
drivers/gpu/drm/i915/intel_display.c		diff \| blob \| blame \| history

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