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ASoC: rockchip: i2s: change bclk and lrck according to sample rates
authorCaesar Wang <wxt@rock-chips.com>
Fri, 6 Nov 2015 11:38:14 +0000 (19:38 +0800)
committerMark Brown <broonie@kernel.org>
Mon, 16 Nov 2015 10:10:24 +0000 (10:10 +0000)
commit2458c37779ddb91b4109949d86f5a5e193ba415b
tree8175fc61436a56646e3b1d4f52f77931e550043etree | snapshot (tar.gz zip)
parent8005c49d9aea74d382f474ce11afbbc7d7130beccommit | diff
ASoC: rockchip: i2s: change bclk and lrck according to sample rates

This patch sets the dividers autonomously.

when i2s works on master mode, and sample rates changed. We need to change
bclk and lrck at the same time for cpu internal side.

As the input source clock to the module is MCLK_I2S,
and by the divider of the module, the clock generator generates
SCLK and LRCK to transmitter and receiver.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
sound/soc/rockchip/rockchip_i2s.c diff | blob | blame | history