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powerpc/mm: e300c2/c3/c4 TLB errata workaround
authorKumar Gala <galak@kernel.crashing.org>
Thu, 19 Mar 2009 03:55:41 +0000 (03:55 +0000)
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>
Tue, 24 Mar 2009 02:47:32 +0000 (13:47 +1100)
commit2319f1239592d0de80414ad2338c2bd7384a2a41
tree805de041dfc84ae9ca767c9767d833977654dbe0tree | snapshot (tar.gz zip)
parenteb3436a0139a651a39dbb37a75b10a2cccd00ad5commit | diff
powerpc/mm: e300c2/c3/c4 TLB errata workaround

Complete workaround for DTLB errata in e300c2/c3/c4 processors.

Due to the bug, the hardware-implemented LRU algorythm always goes to way
1 of the TLB. This fix implements the proposed software workaround in
form of a LRW table for chosing the TLB-way.

Based on patch from David Jander <david@protonic.nl>

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
arch/powerpc/include/asm/mmu.h diff | blob | blame | history
arch/powerpc/kernel/cpu_setup_6xx.S diff | blob | blame | history
arch/powerpc/kernel/cputable.c diff | blob | blame | history
arch/powerpc/kernel/head_32.S diff | blob | blame | history