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clk: si5351: fix .round_rate for multisynth 6-7
authorSergej Sawazki <ce3a@gmx.de>
Mon, 11 May 2015 08:44:50 +0000 (10:44 +0200)
committerMichael Turquette <mturquette@linaro.org>
Wed, 13 May 2015 18:52:05 +0000 (11:52 -0700)
commit2073b5e909b96f8fbc9b8a40b89c1fa316fb092c
treeb203e773113113b7e031455cd203af93cb857ceftree | snapshot (tar.gz zip)
parent81573560150d2f1a6d8433475a3660fcbcf08519commit | diff
clk: si5351: fix .round_rate for multisynth 6-7

The divider calculation for multisynth 6 and 7 differs from the
calculation for multisynth 0-5.

For MS6 and MS7, set MSx_P1 directly, MSx_P1=divide value
[AN619, p. 6].

Referenced document:
[AN619] Manually Generating an Si5351 Register Map, Rev. 0.4

Signed-off-by: Sergej Sawazki <ce3a@gmx.de>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
drivers/clk/clk-si5351.c diff | blob | blame | history