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clk: tegra: Add fixed factor peripheral clock type
authorThierry Reding <treding@nvidia.com>
Mon, 20 Apr 2015 12:34:57 +0000 (14:34 +0200)
committerThierry Reding <treding@nvidia.com>
Thu, 28 Apr 2016 10:41:47 +0000 (12:41 +0200)
commit1ec7032ad517714108cc53a6ee7067276ca21e80
treee852e5e9f0788c4dc448f0c9fe41c43e533a82f8tree | snapshot (tar.gz zip)
parent07314fc108e195044c074f4b443974b5aaa2d5d7commit | diff
clk: tegra: Add fixed factor peripheral clock type

Some of the peripheral clocks on Tegra are derived from one of the top-
level PLLs with a fixed factor. Support these clocks by implementing the
->enable() and ->disable() callbacks using the peripheral clock register
banks and the ->recalc_rate() by dividing the parent rate by the fixed
factor.

Signed-off-by: Thierry Reding <treding@nvidia.com>
drivers/clk/tegra/Makefile diff | blob | blame | history
drivers/clk/tegra/clk-periph-fixed.c [new file with mode: 0644] blob
drivers/clk/tegra/clk.h diff | blob | blame | history