irqchip/gic-v3: Make sure read from ICC_IAR1_EL1 is visible on redestributor
authorTirumalesh Chalamarla <tchalamarla@caviumnetworks.com>
Thu, 4 Feb 2016 18:45:25 +0000 (10:45 -0800)
committerMarc Zyngier <marc.zyngier@arm.com>
Thu, 11 Feb 2016 10:20:02 +0000 (10:20 +0000)
commit1a1ebd5fb1e203ee8cc73508cc7a38ac4b804596
tree5a046e3c634ce678ac7c73e2293bc485024e8eb1
parent389a00d3ad02a06b5d6d692cce76fed6a3dae8b4
irqchip/gic-v3: Make sure read from ICC_IAR1_EL1 is visible on redestributor

The ARM GICv3 specification mentions the need for dsb after a read
from the ICC_IAR1_EL1 register:

4.1.1 Physical CPU Interface:
The effects of reading ICC_IAR0_EL1 and ICC_IAR1_EL1
on the state of a returned INTID are not guaranteed
to be visible until after the execution of a DSB.

Not having this could result in missed interrupts, so let's add the
required barrier.

[Marc: fixed commit message]

Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Tirumalesh Chalamarla <tchalamarla@caviumnetworks.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
arch/arm64/include/asm/arch_gicv3.h