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(parent: b3be457) | patch
clk: mediatek: Fix calculation of PLL rate settings
authorJames Liao <jamesjj.liao@mediatek.com>
Fri, 10 Jul 2015 08:39:33 +0000 (16:39 +0800)
committerStephen Boyd <sboyd@codeaurora.org>
Tue, 28 Jul 2015 18:58:54 +0000 (11:58 -0700)
commit196de71a9d9e9090406a87362d22b67ae633fa7a
tree615be1dddf4c657e5114458cfae75d5e4e6ad6d7tree | snapshot (tar.gz zip)
parentb3be457e5854e3095cd0be850058c765aaf467abcommit | diff
clk: mediatek: Fix calculation of PLL rate settings

Avoid u32 overflow when calculate post divider setting, and
increase the max post divider setting from 3 (/8) to 4 (/16).

Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
drivers/clk/mediatek/clk-pll.c diff | blob | blame | history