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(parent: 3d81d58) | patch
drm/i915: Test coherency of and barriers between cache domains
authorChris Wilson <chris@chris-wilson.co.uk>
Mon, 13 Feb 2017 17:15:32 +0000 (17:15 +0000)
committerChris Wilson <chris@chris-wilson.co.uk>
Mon, 13 Feb 2017 20:45:45 +0000 (20:45 +0000)
commit170594502cf591fd0789d7e5239937b1a87af4c6
tree77757a21dd505037cace248c180f0d79f7c09d00tree | snapshot (tar.gz zip)
parent3d81d589d6e3c89b687771074f65cb8f3b59ccf3commit | diff
drm/i915: Test coherency of and barriers between cache domains

Write into an object using WB, WC, GTT, and GPU paths and make sure that
our internal API is sufficient to ensure coherent reads and writes.

v2: Avoid invalid free upon allocation error

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20170213171558.20942-21-chris@chris-wilson.co.uk
drivers/gpu/drm/i915/i915_gem.c diff | blob | blame | history
drivers/gpu/drm/i915/i915_selftest.h diff | blob | blame | history
drivers/gpu/drm/i915/selftests/i915_gem_coherency.c [new file with mode: 0644] blob
drivers/gpu/drm/i915/selftests/i915_live_selftests.h diff | blob | blame | history