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PCI/ASPM: Add L1 substate capability structure register definitions
authorRajat Jain <rajatja@google.com>
Tue, 3 Jan 2017 06:34:10 +0000 (22:34 -0800)
committerBjorn Helgaas <bhelgaas@google.com>
Fri, 10 Feb 2017 23:14:52 +0000 (17:14 -0600)
commit0fc1223f0e77a748f7040562faaa7027f7db71ca
tree2265dce7f56f188bf4ab7f4db698dcd1d98c43a6tree | snapshot (tar.gz zip)
parent7ce7d89f48834cefece7804d38fc5d85382edf77commit | diff
PCI/ASPM: Add L1 substate capability structure register definitions

Add L1 substate capability structure register definitions for use in
subsequent patches.  See the PCIe r3.1 spec, sec 7.33.

[bhelgaas: add PCIe spec reference]
Signed-off-by: Rajat Jain <rajatja@google.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
include/uapi/linux/pci_regs.h diff | blob | blame | history