clk: sunxi-ng: sun8i-h3: Set CLK_SET_RATE_PARENT for audio module clocks
authorChen-Yu Tsai <wens@csie.org>
Fri, 11 Nov 2016 10:05:58 +0000 (18:05 +0800)
committerMaxime Ripard <maxime.ripard@free-electrons.com>
Fri, 11 Nov 2016 20:47:41 +0000 (21:47 +0100)
commit0f6f9302b819ca352cfd4f42c18ec08d521f9cae
treeafe405ee39f1d01617e691a7d84407c3508581c6
parent937ff9ded8b6ebe8963ade55bdd77a61ded88075
clk: sunxi-ng: sun8i-h3: Set CLK_SET_RATE_PARENT for audio module clocks

The audio module clocks are supposed to be set according to the sample
rate of the audio stream. The audio PLL provides the clock signal for
these module clocks, and only it is freely tunable.

Set CLK_SET_RATE_PARENT for the audio module clocks so their users can
properly tune the clock rate.

Fixes: 0577e4853bfb ("clk: sunxi-ng: Add H3 clocks")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
drivers/clk/sunxi-ng/ccu-sun8i-h3.c