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ARM: mach-ux500: enable 128KB way L2 cache on DB8540
authorMaxime Coquelin <maxime.coquelin@stericsson.com>
Wed, 23 Jan 2013 10:27:58 +0000 (11:27 +0100)
committerLinus Walleij <linus.walleij@linaro.org>
Mon, 18 Mar 2013 12:49:58 +0000 (13:49 +0100)
commit0f2fa40e464c955e928979331625b5485c292bf0
tree670ea27813cf5b9fb5570d0ae6591253bdd51a2etree | snapshot (tar.gz zip)
parentcca438b57e660c9a4a3216a69405b45ff00274e6commit | diff
ARM: mach-ux500: enable 128KB way L2 cache on DB8540

DB8540 L2 was configured with 64KB way size, but it has 128KB as AP9540.

Fix this by modifying ux500_l2x0_init() to use 128KB way size for all
cpus in the x540 family.

Signed-off-by: Maxime Coquelin <maxime.coquelin@stericsson.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Fabio Baltieri <fabio.baltieri@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
arch/arm/mach-ux500/cache-l2x0.c diff | blob | blame | history