clk: tegra: Allow PLLE training to succeed
authorThierry Reding <thierry.reding@avionic-design.de>
Thu, 14 Mar 2013 15:27:05 +0000 (16:27 +0100)
committerMike Turquette <mturquette@linaro.org>
Mon, 1 Apr 2013 18:44:38 +0000 (11:44 -0700)
commit0f1bc12e9eddaba2baf52d020d37670dbabe3702
tree7236ae7d234d20f2dacefd1fb8814d06cb57cdc2
parent07961ac7c0ee8b546658717034fe692fd12eefa9
clk: tegra: Allow PLLE training to succeed

Under some circumstances the PLLE needs to be retrained, in which case
access to the PMC registers is required. Fix this by passing a pointer
to the PMC registers instead of NULL when registering the PLLE clock.

Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
drivers/clk/tegra/clk-tegra20.c