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m68knommu: support version 2 ColdFire split cache
authorGreg Ungerer <gerg@uclinux.org>
Tue, 9 Nov 2010 05:31:08 +0000 (15:31 +1000)
committerGreg Ungerer <gerg@uclinux.org>
Wed, 5 Jan 2011 05:19:20 +0000 (15:19 +1000)
commit0ef6c9b8f7bf62ea05be5b26ee14b18a116b0c2a
tree01ffb12226fef2f4de5f3408e21fe64e19b5a522tree | snapshot (tar.gz zip)
parentd475e3e4739ce465df740b51decbbea3b1b51823commit | diff
m68knommu: support version 2 ColdFire split cache

The newer version 2 ColdFire CPU cores support a configurable cache
arrangement. The cache memory can be used as all instruction cache, all
data cache, or split in half for both instruction and data caching.
Support this setup via a Kconfig time menu that allows a kernel builder
to choose the arrangement they want to use.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>
arch/m68k/include/asm/m52xxacr.h diff | blob | blame | history
arch/m68knommu/Kconfig diff | blob | blame | history
Motorola kernel-slsi