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(parent: 682775b) | patch
powerpc/dts: fix sRIO error interrupt for b4860
authorMinghuan Lian <Minghuan.Lian@freescale.com>
Wed, 31 Jul 2013 02:59:07 +0000 (10:59 +0800)
committerScott Wood <scottwood@freescale.com>
Tue, 29 Oct 2013 02:11:14 +0000 (21:11 -0500)
commit0e3d4373b8a7757a8f5187f5cabafb6aceff469b
tree74108e69667ae0866e066fc63f86f9d10b039793tree | snapshot (tar.gz zip)
parent682775b8de995d97956447730c04d2ff978d4e13commit | diff
powerpc/dts: fix sRIO error interrupt for b4860

For B4 platform, MPIC EISR register is in reversed bitmap order,
instead of "Error interrupt source 0-31. Bit 0 represents SRC0."
the correct ordering is "Error interrupt source 0-31. Bit 0
represents SRC31." This patch is to fix sRIO EISR bit value
of error interrupt in dts node.

Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
arch/powerpc/boot/dts/fsl/b4860si-post.dtsi diff | blob | blame | history