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(parent: d566ebc) | patch
clk: rockchip: rk3368: enable the CLK_SET_RATE_PARENT flag for spdif_8ch
authorzhangqing <zhangqing@rock-chips.com>
Mon, 25 Jan 2016 16:56:01 +0000 (08:56 -0800)
committerHeiko Stuebner <heiko@sntech.de>
Mon, 25 Jan 2016 10:04:51 +0000 (11:04 +0100)
commit0bbe62eb92755ff7c16c859e96a3877de56e32c9
tree717c52dc1c27b2f8541c3749b44e9a288932d272tree | snapshot (tar.gz zip)
parentd566ebc3c06c17b108b5b844f9d08259e3b7ba84commit | diff
clk: rockchip: rk3368: enable the CLK_SET_RATE_PARENT flag for spdif_8ch

SPDIF_8CH set freq need to select parent and calculate parent freq.
so just mark it as the CLK_SET_RATE_PARENT flag.

Signed-off-by: zhangqing <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
drivers/clk/rockchip/clk-rk3368.c diff | blob | blame | history