clk: renesas: rcar-gen3: Add divider support for PLL1 and PLL3
authorGeert Uytterhoeven <geert+renesas@glider.be>
Wed, 19 Jul 2017 14:30:45 +0000 (16:30 +0200)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Wed, 16 Aug 2017 07:51:47 +0000 (09:51 +0200)
commit09a7dea9d58aadda90af5ad4dce1d540fe830868
treec2fa6faccf64d6e758746ca6a5086962986515d1
parent714c53aa2e2d6d60ca1e7d18980767c8b715c288
clk: renesas: rcar-gen3: Add divider support for PLL1 and PLL3

On some R-Car Gen3 SoCs (e.g. R-Car D3), PLL1 and PLL3 use a divider
value different from one.  Extend struct rcar_gen3_cpg_pll_config to handle
this.  As all multipliers and dividers are small, table size increase
can be kept limited by storing them in u8s instead of unsigned ints,
which saves ca. 0.5 KiB for a generic kernel.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
drivers/clk/renesas/r8a7795-cpg-mssr.c
drivers/clk/renesas/r8a7796-cpg-mssr.c
drivers/clk/renesas/rcar-gen3-cpg.c
drivers/clk/renesas/rcar-gen3-cpg.h