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(parent: 46a57af) | patch
drivers: clk: st: Correct the pll-type for A9 for stih418
authorGabriel Fernandez <gabriel.fernandez@linaro.org>
Wed, 7 Oct 2015 09:08:58 +0000 (11:08 +0200)
committerStephen Boyd <sboyd@codeaurora.org>
Fri, 9 Oct 2015 06:52:59 +0000 (23:52 -0700)
commit0829ea5af6d3338c3c5ad0bd377d75a30d6ffc8b
tree4dca0c232d6d48cdd98415ff0c8e46bc167d3563tree | snapshot (tar.gz zip)
parent46a57afdd70c17cf15b2077c5ea611913f80f85fcommit | diff
drivers: clk: st: Correct the pll-type for A9 for stih418

Add support for new PLL-type for stih418 A9-PLL.
Currently the 407_A9_PLL type being used, it is corrected with this patch
4600c28 PLL allows to reach higher frequencies
so its programming algorithm is extended.

Signed-off-by: Pankaj Dev <pankaj.dev@st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt diff | blob | blame | history
drivers/clk/st/clkgen-pll.c diff | blob | blame | history