drm/i915: HSW FBC WaFbcDisableDpfcClockGating
authorRodrigo Vivi <rodrigo.vivi@gmail.com>
Thu, 9 May 2013 17:20:50 +0000 (14:20 -0300)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Fri, 10 May 2013 19:56:50 +0000 (21:56 +0200)
commitd89f2071461d5682b897c73278daaf25fd11aff5
tree7c82a423f5dd3d52a4b88ef6a426eccfb351f092
parent285541647a816e00348916ba7387eeacea30eba9
drm/i915: HSW FBC WaFbcDisableDpfcClockGating

Display register 46500h bit 23 must be set to 1b for the entire time that
Frame Buffer Compression is enabled.

v2: Ville suggested to enable it back when disabling fbc to avoid wasting
    power.

v3: RMW to preserve other bits (by Ville)
v4: Fix from Ville: sed &/| at RMW
v5: Too far on sed.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
[danvet: Insert missing space that checkpatch spotted.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_pm.c