projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: c09b47d) | patch
[MIPS] Fix handling of 0 length I & D caches.
authorChris Dearman <chris@mips.com>
Tue, 20 Jun 2006 17:06:52 +0000 (18:06 +0100)
committerRalf Baechle <ralf@linux-mips.org>
Thu, 29 Jun 2006 20:10:53 +0000 (21:10 +0100)
commit73f403527b9ec5367376076eafb3d2f505d8e2e3
treebc3f080e75661231d9f30ecb385193bb57f8bc4etree | snapshot (tar.gz zip)
parentc09b47d8a99104897afd682b48f292e05461a0c2commit | diff
[MIPS] Fix handling of 0 length I & D caches.

Don't ask.

Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/mm/c-r4k.c diff | blob | blame | history
kernel source for telekom puls (alcatel/mediatek)