X-Git-Url: https://git.stricted.de/?a=blobdiff_plain;ds=sidebyside;f=arch%2Fmips%2Finclude%2Fasm%2Fcpu-features.h;h=089125a6ae6a019bcfb051b957a9b4547aea4c0c;hb=da4b62cd6762ce327f660c6e45c8d5a739197159;hp=ca400f7c3f594944d31a7b1341b6aa04d7e4c757;hpb=78ab952717b62c0ba6ca7f7a27eaa0486685e45f;p=GitHub%2Fmt8127%2Fandroid_kernel_alcatel_ttab.git

diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index ca400f7c3f59..089125a6ae6a 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -95,8 +95,8 @@
 #ifndef cpu_has_smartmips
 #define cpu_has_smartmips      (cpu_data[0].ases & MIPS_ASE_SMARTMIPS)
 #endif
-#ifndef kernel_uses_smartmips_rixi
-#define kernel_uses_smartmips_rixi 0
+#ifndef cpu_has_rixi
+#define cpu_has_rixi		(cpu_data[0].options & MIPS_CPU_RIXI)
 #endif
 #ifndef cpu_has_vtag_icache
 #define cpu_has_vtag_icache	(cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
@@ -252,4 +252,8 @@
 #define cpu_hwrena_impl_bits		0
 #endif
 
+#ifndef cpu_has_perf_cntr_intr_bit
+#define cpu_has_perf_cntr_intr_bit	(cpu_data[0].options & MIPS_CPU_PCI)
+#endif
+
 #endif /* __ASM_CPU_FEATURES_H */