drm/i915: Pad GTT views of exec objects up to user specified size

[GitHub/LineageOS/android_kernel_motorola_exynos9610.git] / include / uapi / drm / i915_drm.h

diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index a5524cc95ff8b6acd1c7a79bb554b0f24cf7bc42..0f292733cffcf43027f925008931590d472cfd2a 100644 (file)
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -29,6 +29,10 @@
 
 #include "drm.h"
 
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
 /* Please note that modifications to all structs defined here are
  * subject to backwards-compatibility constraints.
  */
@@ -58,6 +62,30 @@
 #define I915_ERROR_UEVENT              "ERROR"
 #define I915_RESET_UEVENT              "RESET"
 
+/*
+ * MOCS indexes used for GPU surfaces, defining the cacheability of the
+ * surface data and the coherency for this data wrt. CPU vs. GPU accesses.
+ */
+enum i915_mocs_table_index {
+       /*
+        * Not cached anywhere, coherency between CPU and GPU accesses is
+        * guaranteed.
+        */
+       I915_MOCS_UNCACHED,
+       /*
+        * Cacheability and coherency controlled by the kernel automatically
+        * based on the DRM_I915_GEM_SET_CACHING IOCTL setting and the current
+        * usage of the surface (used for display scanout or not).
+        */
+       I915_MOCS_PTE,
+       /*
+        * Cached in all GPU caches available on the platform.
+        * Coherency between CPU and GPU accesses to the surface is not
+        * guaranteed without extra synchronization.
+        */
+       I915_MOCS_CACHED,
+};
+
 /* Each region is a minimum of 16k, and there are at most 255 of them.
  */
 #define I915_NR_TEX_REGIONS 255        /* table size 2k - maximum due to use
@@ -357,6 +385,8 @@ typedef struct drm_i915_irq_wait {
 #define I915_PARAM_HAS_GPU_RESET        35
 #define I915_PARAM_HAS_RESOURCE_STREAMER 36
 #define I915_PARAM_HAS_EXEC_SOFTPIN     37
+#define I915_PARAM_HAS_POOLED_EU        38
+#define I915_PARAM_MIN_EU_IN_POOL       39
 
 typedef struct drm_i915_getparam {
        __s32 param;
@@ -692,15 +722,20 @@ struct drm_i915_gem_exec_object2 {
         */
        __u64 offset;
 
-#define EXEC_OBJECT_NEEDS_FENCE (1<<0)
-#define EXEC_OBJECT_NEEDS_GTT  (1<<1)
-#define EXEC_OBJECT_WRITE      (1<<2)
+#define EXEC_OBJECT_NEEDS_FENCE                 (1<<0)
+#define EXEC_OBJECT_NEEDS_GTT           (1<<1)
+#define EXEC_OBJECT_WRITE               (1<<2)
 #define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3)
-#define EXEC_OBJECT_PINNED     (1<<4)
-#define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_PINNED<<1)
+#define EXEC_OBJECT_PINNED              (1<<4)
+#define EXEC_OBJECT_PAD_TO_SIZE                 (1<<5)
+/* All remaining bits are MBZ and RESERVED FOR FUTURE USE */
+#define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_PAD_TO_SIZE<<1)
        __u64 flags;
 
-       __u64 rsvd1;
+       union {
+               __u64 rsvd1;
+               __u64 pad_to_size;
+       };
        __u64 rsvd2;
 };
 
@@ -1167,7 +1202,12 @@ struct drm_i915_gem_context_param {
 #define I915_CONTEXT_PARAM_BAN_PERIOD  0x1
 #define I915_CONTEXT_PARAM_NO_ZEROMAP  0x2
 #define I915_CONTEXT_PARAM_GTT_SIZE    0x3
+#define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE    0x4
        __u64 value;
 };
 
+#if defined(__cplusplus)
+}
+#endif
+
 #endif /* _UAPI_I915_DRM_H_ */