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import PULS_20160108
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / include / linux / topology.h
diff --git a/include/linux/topology.h b/include/linux/topology.h
index d3cf0d6e7712c115fb529559b59c2ae4f6f8cd9c..576c4138a1f33c105cbc13b5f25a29ce9b8ddb9b 100644 (file)
--- a/include/linux/topology.h
+++ b/include/linux/topology.h
@@ -113,6 +113,31 @@ int arch_update_cpu_topology(void);
 #ifdef CONFIG_SCHED_MC
 /* Common values for MC siblings. for now mostly derived from SD_CPU_INIT */
 #ifndef SD_MC_INIT
+#ifdef CONFIG_MT_LOAD_BALANCE_ENHANCEMENT
+#define SD_MC_INIT (struct sched_domain) {                             \
+       .min_interval           = 1,                                    \
+       .max_interval           = 4,                                    \
+       .busy_factor            = 64,                                   \
+       .imbalance_pct          = 125,                                  \
+       .cache_nice_tries       = 1,                                    \
+       .busy_idx               = 2,                                    \
+       .wake_idx               = 0,                                    \
+       .forkexec_idx           = 0,                                    \
+                                                                       \
+       .flags                  = 1*SD_LOAD_BALANCE                     \
+                               | 1*SD_BALANCE_NEWIDLE                  \
+                               | 1*SD_BALANCE_EXEC                     \
+                               | 1*SD_BALANCE_FORK                     \
+                               | 1*SD_BALANCE_WAKE                     \
+                               | 0*SD_WAKE_AFFINE                      \
+                               | 0*SD_SHARE_CPUPOWER                   \
+                               | 1*SD_SHARE_PKG_RESOURCES              \
+                               | 0*SD_SERIALIZE                        \
+                               ,                                       \
+       .last_balance           = jiffies,                              \
+       .balance_interval       = 1,                                    \
+}
+#else
 #define SD_MC_INIT (struct sched_domain) {                             \
        .min_interval           = 1,                                    \
        .max_interval           = 4,                                    \
@@ -137,10 +162,163 @@ int arch_update_cpu_topology(void);
        .balance_interval       = 1,                                    \
 }
 #endif
+#endif
 #endif /* CONFIG_SCHED_MC */
 
 /* Common values for CPUs */
 #ifndef SD_CPU_INIT
+# ifdef CONFIG_MT_LOAD_BALANCE_ENHANCEMENT
+#  ifdef CONFIG_MTK_SCHED_CMP_TGS
+#   ifdef CONFIG_MTK_SCHED_CMP_PACK_SMALL_TASK
+#define SD_CPU_INIT (struct sched_domain) {                            \
+       .min_interval           = 1,                                    \
+       .max_interval           = 4,                                    \
+       .busy_factor            = 64,                                   \
+       .imbalance_pct          = 125,                                  \
+       .cache_nice_tries       = 1,                                    \
+       .busy_idx               = 2,                                    \
+       .idle_idx               = 1,                                    \
+       .newidle_idx            = 0,                                    \
+       .wake_idx               = 0,                                    \
+       .forkexec_idx           = 0,                                    \
+                                                                       \
+       .flags                  = 1*SD_LOAD_BALANCE                     \
+                               | 1*SD_BALANCE_NEWIDLE                  \
+                               | 1*SD_BALANCE_EXEC                     \
+                               | 1*SD_BALANCE_FORK                     \
+                               | 1*SD_BALANCE_WAKE                     \
+                               | 0*SD_WAKE_AFFINE                      \
+                               | 0*SD_SHARE_CPUPOWER                   \
+                               | 0*SD_SHARE_PKG_RESOURCES              \
+                               | 0*SD_SERIALIZE                        \
+                               | 1*SD_PREFER_SIBLING                   \
+                               | arch_sd_share_power_line()    \
+                               | 1*SD_BALANCE_TG       \
+                               ,                                       \
+       .last_balance           = jiffies,                              \
+       .balance_interval       = 1,                                    \
+}
+#   else  
+#define SD_CPU_INIT (struct sched_domain) {                            \
+       .min_interval           = 1,                                    \
+       .max_interval           = 4,                                    \
+       .busy_factor            = 64,                                   \
+       .imbalance_pct          = 125,                                  \
+       .cache_nice_tries       = 1,                                    \
+       .busy_idx               = 2,                                    \
+       .idle_idx               = 1,                                    \
+       .newidle_idx            = 0,                                    \
+       .wake_idx               = 0,                                    \
+       .forkexec_idx           = 0,                                    \
+                                                                       \
+       .flags                  = 1*SD_LOAD_BALANCE                     \
+                               | 1*SD_BALANCE_NEWIDLE                  \
+                               | 1*SD_BALANCE_EXEC                     \
+                               | 1*SD_BALANCE_FORK                     \
+                               | 1*SD_BALANCE_WAKE                     \
+                               | 0*SD_WAKE_AFFINE                      \
+                               | 0*SD_SHARE_CPUPOWER                   \
+                               | 0*SD_SHARE_PKG_RESOURCES              \
+                               | 0*SD_SERIALIZE                        \
+                               | 1*SD_PREFER_SIBLING                   \
+                               | 1*SD_BALANCE_TG       \
+                               ,                                       \
+       .last_balance           = jiffies,                              \
+       .balance_interval       = 1,                                    \
+}
+#   endif 
+#  else
+#   ifdef CONFIG_MTK_SCHED_CMP_PACK_SMALL_TASK
+#define SD_CPU_INIT (struct sched_domain) {                            \
+       .min_interval           = 1,                                    \
+       .max_interval           = 4,                                    \
+       .busy_factor            = 64,                                   \
+       .imbalance_pct          = 125,                                  \
+       .cache_nice_tries       = 1,                                    \
+       .busy_idx               = 2,                                    \
+       .idle_idx               = 1,                                    \
+       .newidle_idx            = 0,                                    \
+       .wake_idx               = 0,                                    \
+       .forkexec_idx           = 0,                                    \
+                                                                       \
+       .flags                  = 1*SD_LOAD_BALANCE                     \
+                               | 1*SD_BALANCE_NEWIDLE                  \
+                               | 1*SD_BALANCE_EXEC                     \
+                               | 1*SD_BALANCE_FORK                     \
+                               | 1*SD_BALANCE_WAKE                     \
+                               | 0*SD_WAKE_AFFINE                      \
+                               | 0*SD_SHARE_CPUPOWER                   \
+                               | 0*SD_SHARE_PKG_RESOURCES              \
+                               | 0*SD_SERIALIZE                        \
+                               | 1*SD_PREFER_SIBLING                   \
+                               | arch_sd_share_power_line()    \
+                               ,                                       \
+       .last_balance           = jiffies,                              \
+       .balance_interval       = 1,                                    \
+}
+#   else
+#define SD_CPU_INIT (struct sched_domain) {                            \
+       .min_interval           = 1,                                    \
+       .max_interval           = 4,                                    \
+       .busy_factor            = 64,                                   \
+       .imbalance_pct          = 125,                                  \
+       .cache_nice_tries       = 1,                                    \
+       .busy_idx               = 2,                                    \
+       .idle_idx               = 1,                                    \
+       .newidle_idx            = 0,                                    \
+       .wake_idx               = 0,                                    \
+       .forkexec_idx           = 0,                                    \
+                                                                       \
+       .flags                  = 1*SD_LOAD_BALANCE                     \
+                               | 1*SD_BALANCE_NEWIDLE                  \
+                               | 1*SD_BALANCE_EXEC                     \
+                               | 1*SD_BALANCE_FORK                     \
+                               | 1*SD_BALANCE_WAKE                     \
+                               | 0*SD_WAKE_AFFINE                      \
+                               | 0*SD_SHARE_CPUPOWER                   \
+                               | 0*SD_SHARE_PKG_RESOURCES              \
+                               | 0*SD_SERIALIZE                        \
+                               | 1*SD_PREFER_SIBLING                   \
+                               ,                                       \
+       .last_balance           = jiffies,                              \
+       .balance_interval       = 1,                                    \
+}
+#   endif
+#  endif
+
+# else  //CONFIG_MT_LOAD_BALANCE_ENHANCEMENT
+
+#  ifdef CONFIG_MTK_SCHED_CMP_TGS
+#   ifdef CONFIG_MTK_SCHED_CMP_PACK_SMALL_TASK
+#define SD_CPU_INIT (struct sched_domain) {                            \
+       .min_interval           = 1,                                    \
+       .max_interval           = 4,                                    \
+       .busy_factor            = 64,                                   \
+       .imbalance_pct          = 125,                                  \
+       .cache_nice_tries       = 1,                                    \
+       .busy_idx               = 2,                                    \
+       .idle_idx               = 1,                                    \
+       .newidle_idx            = 0,                                    \
+       .wake_idx               = 0,                                    \
+       .forkexec_idx           = 0,                                    \
+                                                                       \
+       .flags                  = 1*SD_LOAD_BALANCE                     \
+                               | 1*SD_BALANCE_NEWIDLE                  \
+                               | 1*SD_BALANCE_EXEC                     \
+                               | 1*SD_BALANCE_FORK                     \
+                               | 0*SD_BALANCE_WAKE                     \
+                               | 1*SD_WAKE_AFFINE                      \
+                               | 0*SD_SHARE_CPUPOWER                   \
+                               | 0*SD_SHARE_PKG_RESOURCES              \
+                               | 0*SD_SERIALIZE                        \
+                               | 1*SD_PREFER_SIBLING                   \
+                               | arch_sd_share_power_line()    \
+                               | 1*SD_BALANCE_TG       \
+                               ,                                       \
+       .last_balance           = jiffies,                              \
+       .balance_interval       = 1,                                    \
+}
+#   else
 #define SD_CPU_INIT (struct sched_domain) {                            \
        .min_interval           = 1,                                    \
        .max_interval           = 4,                                    \
@@ -163,10 +341,72 @@ int arch_update_cpu_topology(void);
                                | 0*SD_SHARE_PKG_RESOURCES              \
                                | 0*SD_SERIALIZE                        \
                                | 1*SD_PREFER_SIBLING                   \
+                               | 1*SD_BALANCE_TG       \
                                ,                                       \
        .last_balance           = jiffies,                              \
        .balance_interval       = 1,                                    \
 }
+#   endif
+#  else
+#   ifdef CONFIG_MTK_SCHED_CMP_PACK_SMALL_TASK
+#define SD_CPU_INIT (struct sched_domain) {                            \
+       .min_interval           = 1,                                    \
+       .max_interval           = 4,                                    \
+       .busy_factor            = 64,                                   \
+       .imbalance_pct          = 125,                                  \
+       .cache_nice_tries       = 1,                                    \
+       .busy_idx               = 2,                                    \
+       .idle_idx               = 1,                                    \
+       .newidle_idx            = 0,                                    \
+       .wake_idx               = 0,                                    \
+       .forkexec_idx           = 0,                                    \
+                                                                       \
+       .flags                  = 1*SD_LOAD_BALANCE                     \
+                               | 1*SD_BALANCE_NEWIDLE                  \
+                               | 1*SD_BALANCE_EXEC                     \
+                               | 1*SD_BALANCE_FORK                     \
+                               | 0*SD_BALANCE_WAKE                     \
+                               | 1*SD_WAKE_AFFINE                      \
+                               | 0*SD_SHARE_CPUPOWER                   \
+                               | 0*SD_SHARE_PKG_RESOURCES              \
+                               | 0*SD_SERIALIZE                        \
+                               | 1*SD_PREFER_SIBLING                   \
+                               | arch_sd_share_power_line()    \
+                               ,                                       \
+       .last_balance           = jiffies,                              \
+       .balance_interval       = 1,                                    \
+}
+#   else
+#define SD_CPU_INIT (struct sched_domain) {                            \
+       .min_interval           = 1,                                    \
+       .max_interval           = 4,                                    \
+       .busy_factor            = 64,                                   \
+       .imbalance_pct          = 125,                                  \
+       .cache_nice_tries       = 1,                                    \
+       .busy_idx               = 2,                                    \
+       .idle_idx               = 1,                                    \
+       .newidle_idx            = 0,                                    \
+       .wake_idx               = 0,                                    \
+       .forkexec_idx           = 0,                                    \
+                                                                       \
+       .flags                  = 1*SD_LOAD_BALANCE                     \
+                               | 1*SD_BALANCE_NEWIDLE                  \
+                               | 1*SD_BALANCE_EXEC                     \
+                               | 1*SD_BALANCE_FORK                     \
+                               | 0*SD_BALANCE_WAKE                     \
+                               | 1*SD_WAKE_AFFINE                      \
+                               | 0*SD_SHARE_CPUPOWER                   \
+                               | 0*SD_SHARE_PKG_RESOURCES              \
+                               | 0*SD_SERIALIZE                        \
+                               | 1*SD_PREFER_SIBLING                   \
+                               ,                                       \
+       .last_balance           = jiffies,                              \
+       .balance_interval       = 1,                                    \
+}
+#   endif
+#  endif
+
+# endif //CONFIG_MT_LOAD_BALANCE_ENHANCEMENT
 #endif
 
 #ifdef CONFIG_SCHED_BOOK
kernel source for telekom puls (alcatel/mediatek)