[S390] Cleanup page table definitions.

[GitHub/mt8127/android_kernel_alcatel_ttab.git] / include / asm-s390 / mmu_context.h

diff --git a/include/asm-s390/mmu_context.h b/include/asm-s390/mmu_context.h
index 1d21da220d49b8779ad3e916d67c54dfc1f73547..05b842126b993295d95912c8f057f5cb182c5397 100644 (file)
--- a/include/asm-s390/mmu_context.h
+++ b/include/asm-s390/mmu_context.h
@@ -10,6 +10,8 @@
 #define __S390_MMU_CONTEXT_H
 
 #include <asm/pgalloc.h>
+#include <asm-generic/mm_hooks.h>
+
 /*
  * get a new mmu context.. S390 don't know about contexts.
  */
@@ -19,45 +21,43 @@
 
 #ifndef __s390x__
 #define LCTL_OPCODE "lctl"
-#define PGTABLE_BITS (_SEGMENT_TABLE|USER_STD_MASK)
 #else
 #define LCTL_OPCODE "lctlg"
-#define PGTABLE_BITS (_REGION_TABLE|USER_STD_MASK)
 #endif
 
-static inline void enter_lazy_tlb(struct mm_struct *mm,
-                                  struct task_struct *tsk)
+static inline void update_mm(struct mm_struct *mm, struct task_struct *tsk)
 {
+       pgd_t *pgd = mm->pgd;
+       unsigned long asce_bits;
+
+       /* Calculate asce bits from the first pgd table entry. */
+       asce_bits = _ASCE_TABLE_LENGTH | _ASCE_USER_BITS;
+#ifdef CONFIG_64BIT
+       asce_bits |= _ASCE_TYPE_REGION3;
+#endif
+       S390_lowcore.user_asce = asce_bits | __pa(pgd);
+       if (switch_amode) {
+               /* Load primary space page table origin. */
+               pgd_t *shadow_pgd = get_shadow_table(pgd) ? : pgd;
+               S390_lowcore.user_exec_asce = asce_bits | __pa(shadow_pgd);
+               asm volatile(LCTL_OPCODE" 1,1,%0\n"
+                            : : "m" (S390_lowcore.user_exec_asce) );
+       } else
+               /* Load home space page table origin. */
+               asm volatile(LCTL_OPCODE" 13,13,%0"
+                            : : "m" (S390_lowcore.user_asce) );
 }
 
 static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
                             struct task_struct *tsk)
 {
-       pgd_t *shadow_pgd = get_shadow_pgd(next->pgd);
-
-       if (prev != next) {
-               S390_lowcore.user_asce = (__pa(next->pgd) & PAGE_MASK) |
-                                        PGTABLE_BITS;
-               if (shadow_pgd) {
-                       /* Load primary/secondary space page table origin. */
-                       S390_lowcore.user_exec_asce =
-                               (__pa(shadow_pgd) & PAGE_MASK) | PGTABLE_BITS;
-                       asm volatile(LCTL_OPCODE" 1,1,%0\n"
-                                    LCTL_OPCODE" 7,7,%1"
-                                    : : "m" (S390_lowcore.user_exec_asce),
-                                        "m" (S390_lowcore.user_asce) );
-               } else if (switch_amode) {
-                       /* Load primary space page table origin. */
-                       asm volatile(LCTL_OPCODE" 1,1,%0"
-                                    : : "m" (S390_lowcore.user_asce) );
-               } else
-                       /* Load home space page table origin. */
-                       asm volatile(LCTL_OPCODE" 13,13,%0"
-                                    : : "m" (S390_lowcore.user_asce) );
-       }
+       if (unlikely(prev == next))
+               return;
        cpu_set(smp_processor_id(), next->cpu_vm_mask);
+       update_mm(next, tsk);
 }
 
+#define enter_lazy_tlb(mm,tsk) do { } while (0)
 #define deactivate_mm(tsk,mm)  do { } while (0)
 
 static inline void activate_mm(struct mm_struct *prev,