Merge tag 'pci-v3.13-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaa...

[GitHub/exynos8895/android_kernel_samsung_universal8895.git] / drivers / staging / et131x / et131x.c

diff --git a/drivers/staging/et131x/et131x.c b/drivers/staging/et131x/et131x.c
index 820a332f31886d7fc0def83840d1a3b267d78562..ab8b29d2cb2609d3c19bd5d3dddfdbdbdc0c98e2 100644 (file)
--- a/drivers/staging/et131x/et131x.c
+++ b/drivers/staging/et131x/et131x.c
@@ -3601,17 +3601,10 @@ static int et131x_pci_init(struct et131x_adapter *adapter,
                goto err_out;
        }
 
-       /* Let's set up the PORT LOGIC Register.  First we need to know what
-        * the max_payload_size is
-        */
-       if (pcie_capability_read_word(pdev, PCI_EXP_DEVCAP, &max_payload)) {
-               dev_err(&pdev->dev,
-                   "Could not read PCI config space for Max Payload Size\n");
-               goto err_out;
-       }
+       /* Let's set up the PORT LOGIC Register. */
 
        /* Program the Ack/Nak latency and replay timers */
-       max_payload &= 0x07;
+       max_payload = pdev->pcie_mpss;
 
        if (max_payload < 2) {
                static const u16 acknak[2] = { 0x76, 0xD0 };
@@ -3641,8 +3634,7 @@ static int et131x_pci_init(struct et131x_adapter *adapter,
        }
 
        /* Change the max read size to 2k */
-       if (pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL,
-                               PCI_EXP_DEVCTL_READRQ, 0x4 << 12)) {
+       if (pcie_set_readrq(pdev, 2048)) {
                dev_err(&pdev->dev,
                        "Couldn't change PCI config space for Max read size\n");
                goto err_out;