staging: brcm80211: Purge linuxver.h and redistribute #includes as required

[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / staging / brcm80211 / util / sbutils.c

diff --git a/drivers/staging/brcm80211/util/sbutils.c b/drivers/staging/brcm80211/util/sbutils.c
index acb78a01bd3d6f20a06e6a5daac4a60f996659ae..82767e266e970d9e741d424a6c98a53e70d7ffb9 100644 (file)
--- a/drivers/staging/brcm80211/util/sbutils.c
+++ b/drivers/staging/brcm80211/util/sbutils.c
@@ -14,8 +14,11 @@
  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  */
 
-#include <typedefs.h>
+#include <linux/types.h>
 #include <bcmdefs.h>
+#ifdef BRCM_FULLMAC
+#include <linux/netdevice.h>
+#endif
 #include <osl.h>
 #include <bcmutils.h>
 #include <siutils.h>
@@ -72,7 +75,7 @@ uint sb_coreid(si_t *sih)
 }
 
 /* return core index of the core with address 'sba' */
-static uint BCMATTACHFN(_sb_coreidx) (si_info_t *sii, u32 sba)
+static uint _sb_coreidx(si_info_t *sii, u32 sba)
 {
        uint i;
 
@@ -83,14 +86,14 @@ static uint BCMATTACHFN(_sb_coreidx) (si_info_t *sii, u32 sba)
 }
 
 /* return core address of the current core */
-static u32 BCMATTACHFN(_sb_coresba) (si_info_t *sii)
+static u32 _sb_coresba(si_info_t *sii)
 {
        u32 sbaddr = 0;
 
        switch (BUSTYPE(sii->pub.bustype)) {
        case SPI_BUS:
        case SDIO_BUS:
-               sbaddr = (u32) (uintptr) sii->curmap;
+               sbaddr = (u32)(unsigned long)sii->curmap;
                break;
        default:
                ASSERT(0);
@@ -145,7 +148,7 @@ uint sb_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val)
        u32 *r = NULL;
        uint w;
        uint intr_val = 0;
-       bool fast = FALSE;
+       bool fast = false;
        si_info_t *sii;
 
        sii = SI_INFO(sih);
@@ -205,9 +208,9 @@ uint sb_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val)
  * starting from bus 'sbba', inclusive.
  */
 #define SB_MAXBUSES    2
-static uint
-BCMATTACHFN(_sb_scan) (si_info_t *sii, u32 sba, void *regs, uint bus,
-                      u32 sbba, uint numcores) {
+static uint _sb_scan(si_info_t *sii, u32 sba, void *regs, uint bus, u32 sbba,
+                    uint numcores)
+{
        uint next;
        uint ncc = 0;
        uint i;
@@ -287,7 +290,7 @@ BCMATTACHFN(_sb_scan) (si_info_t *sii, u32 sba, void *regs, uint bus,
 }
 
 /* scan the sb enumerated space to identify all cores */
-void BCMATTACHFN(sb_scan) (si_t *sih, void *regs, uint devid)
+void sb_scan(si_t *sih, void *regs, uint devid)
 {
        si_info_t *sii;
        u32 origsba;
@@ -350,7 +353,7 @@ static void *_sb_setcoreidx(si_info_t *sii, uint coreidx)
        case SDIO_BUS:
                /* map new one */
                if (!sii->regs[coreidx]) {
-                       sii->regs[coreidx] = (void *)(uintptr) sbaddr;
+                       sii->regs[coreidx] = (void *)sbaddr;
                        ASSERT(GOODREGS(sii->regs[coreidx]));
                }
                regs = sii->regs[coreidx];
@@ -402,7 +405,7 @@ bool sb_taclear(si_t *sih, bool details)
        sbconfig_t *sb;
        uint origidx;
        uint intr_val = 0;
-       bool rc = FALSE;
+       bool rc = false;
        u32 inband = 0, serror = 0, timeout = 0;
        void *corereg = NULL;
        volatile u32 imstate, tmstate;
@@ -445,7 +448,7 @@ bool sb_taclear(si_t *sih, bool details)
        }
 
        if (inband | timeout | serror) {
-               rc = TRUE;
+               rc = true;
                SI_ERROR(("sb_taclear: inband 0x%x, serror 0x%x, timeout "
                        "0x%x!\n", inband, serror, timeout));
        }
@@ -477,7 +480,7 @@ void sb_core_disable(si_t *sih, u32 bits)
           (preserve core-specific bits) */
        OR_SBREG(sii, &sb->sbtmstatelow, SBTML_REJ);
        dummy = R_SBREG(sii, &sb->sbtmstatelow);
-       OSL_DELAY(1);
+       udelay(1);
        SPINWAIT((R_SBREG(sii, &sb->sbtmstatehigh) & SBTMH_BUSY), 100000);
        if (R_SBREG(sii, &sb->sbtmstatehigh) & SBTMH_BUSY)
                SI_ERROR(("%s: target state still busy\n", __func__));
@@ -485,7 +488,7 @@ void sb_core_disable(si_t *sih, u32 bits)
        if (R_SBREG(sii, &sb->sbidlow) & SBIDL_INIT) {
                OR_SBREG(sii, &sb->sbimstate, SBIM_RJ);
                dummy = R_SBREG(sii, &sb->sbimstate);
-               OSL_DELAY(1);
+               udelay(1);
                SPINWAIT((R_SBREG(sii, &sb->sbimstate) & SBIM_BY), 100000);
        }
 
@@ -494,7 +497,7 @@ void sb_core_disable(si_t *sih, u32 bits)
                (((bits | SICF_FGC | SICF_CLOCK_EN) << SBTML_SICF_SHIFT) |
                 SBTML_REJ | SBTML_RESET));
        dummy = R_SBREG(sii, &sb->sbtmstatelow);
-       OSL_DELAY(10);
+       udelay(10);
 
        /* don't forget to clear the initiator reject bit */
        if (R_SBREG(sii, &sb->sbidlow) & SBIDL_INIT)
@@ -504,7 +507,7 @@ disable:
        /* leave reset and reject asserted */
        W_SBREG(sii, &sb->sbtmstatelow,
                ((bits << SBTML_SICF_SHIFT) | SBTML_REJ | SBTML_RESET));
-       OSL_DELAY(1);
+       udelay(1);
 }
 
 /* reset and re-enable a core
@@ -538,7 +541,7 @@ void sb_core_reset(si_t *sih, u32 bits, u32 resetbits)
                (((bits | resetbits | SICF_FGC | SICF_CLOCK_EN) <<
                  SBTML_SICF_SHIFT) | SBTML_RESET));
        dummy = R_SBREG(sii, &sb->sbtmstatelow);
-       OSL_DELAY(1);
+       udelay(1);
 
        if (R_SBREG(sii, &sb->sbtmstatehigh) & SBTMH_SERR)
                W_SBREG(sii, &sb->sbtmstatehigh, 0);
@@ -552,13 +555,13 @@ void sb_core_reset(si_t *sih, u32 bits, u32 resetbits)
                ((bits | resetbits | SICF_FGC | SICF_CLOCK_EN) <<
                 SBTML_SICF_SHIFT));
        dummy = R_SBREG(sii, &sb->sbtmstatelow);
-       OSL_DELAY(1);
+       udelay(1);
 
        /* leave clock enabled */
        W_SBREG(sii, &sb->sbtmstatelow,
                ((bits | SICF_CLOCK_EN) << SBTML_SICF_SHIFT));
        dummy = R_SBREG(sii, &sb->sbtmstatelow);
-       OSL_DELAY(1);
+       udelay(1);
 }
 
 u32 sb_base(u32 admatch)