Merge tag 'powerpc-4.12-2' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc...

[GitHub/LineageOS/android_kernel_motorola_exynos9610.git] / drivers / pinctrl / sh-pfc / pfc-r8a7791.c

diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
index 841cecdca7ea34c49c0245519b5a4cd86c4bf3da..2ed7eeb50aac2c197016e4916ea7fcc002b886bf 100644 (file)
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
@@ -203,7 +203,7 @@ enum {
 
        /* IPSR6 */
        FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B,
-       FN_SCIF_CLK, FN_BPFCLK_E,
+       FN_SCIF_CLK, FN_DVC_MUTE, FN_BPFCLK_E,
        FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2,
        FN_SCIFA2_RXD, FN_FMIN_E,
        FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD,
@@ -573,7 +573,7 @@ enum {
 
        /* IPSR6 */
        AUDIO_CLKB_MARK, STP_OPWM_0_B_MARK, MSIOF1_SCK_B_MARK,
-       SCIF_CLK_MARK, BPFCLK_E_MARK,
+       SCIF_CLK_MARK, DVC_MUTE_MARK, BPFCLK_E_MARK,
        AUDIO_CLKC_MARK, SCIFB0_SCK_C_MARK, MSIOF1_SYNC_B_MARK, RX2_MARK,
        SCIFA2_RXD_MARK, FMIN_E_MARK,
        AUDIO_CLKOUT_MARK, MSIOF1_SS1_B_MARK, TX2_MARK, SCIFA2_TXD_MARK,
@@ -1010,14 +1010,17 @@ static const u16 pinmux_data[] = {
        PINMUX_IPSR_MSEL(IP4_12_10, SCL2, SEL_IIC2_0),
        PINMUX_IPSR_MSEL(IP4_12_10, GPS_CLK_B, SEL_GPS_1),
        PINMUX_IPSR_MSEL(IP4_12_10, GLO_Q0_D, SEL_GPS_3),
+       PINMUX_IPSR_MSEL(IP4_12_10, HSCK1_E, SEL_HSCIF1_4),
        PINMUX_IPSR_GPSR(IP4_15_13, SSI_WS2),
        PINMUX_IPSR_MSEL(IP4_15_13, SDA2, SEL_IIC2_0),
        PINMUX_IPSR_MSEL(IP4_15_13, GPS_SIGN_B, SEL_GPS_1),
        PINMUX_IPSR_MSEL(IP4_15_13, RX2_E, SEL_SCIF2_4),
        PINMUX_IPSR_MSEL(IP4_15_13, GLO_Q1_D, SEL_GPS_3),
+       PINMUX_IPSR_MSEL(IP4_15_13, HCTS1_N_E, SEL_HSCIF1_4),
        PINMUX_IPSR_GPSR(IP4_18_16, SSI_SDATA2),
        PINMUX_IPSR_MSEL(IP4_18_16, GPS_MAG_B, SEL_GPS_1),
        PINMUX_IPSR_MSEL(IP4_18_16, TX2_E, SEL_SCIF2_4),
+       PINMUX_IPSR_MSEL(IP4_18_16, HRTS1_N_E, SEL_HSCIF1_4),
        PINMUX_IPSR_GPSR(IP4_19, SSI_SCK34),
        PINMUX_IPSR_GPSR(IP4_20, SSI_WS34),
        PINMUX_IPSR_GPSR(IP4_21, SSI_SDATA3),
@@ -1090,6 +1093,7 @@ static const u16 pinmux_data[] = {
        PINMUX_IPSR_MSEL(IP6_2_0, STP_OPWM_0_B, SEL_SSP_1),
        PINMUX_IPSR_MSEL(IP6_2_0, MSIOF1_SCK_B, SEL_SOF1_1),
        PINMUX_IPSR_MSEL(IP6_2_0, SCIF_CLK, SEL_SCIF_0),
+       PINMUX_IPSR_GPSR(IP6_2_0, DVC_MUTE),
        PINMUX_IPSR_MSEL(IP6_2_0, BPFCLK_E, SEL_FM_4),
        PINMUX_IPSR_GPSR(IP6_5_3, AUDIO_CLKC),
        PINMUX_IPSR_MSEL(IP6_5_3, SCIFB0_SCK_C, SEL_SCIFB_2),
@@ -1099,7 +1103,7 @@ static const u16 pinmux_data[] = {
        PINMUX_IPSR_MSEL(IP6_5_3, FMIN_E, SEL_FM_4),
        PINMUX_IPSR_GPSR(IP6_7_6, AUDIO_CLKOUT),
        PINMUX_IPSR_MSEL(IP6_7_6, MSIOF1_SS1_B, SEL_SOF1_1),
-       PINMUX_IPSR_MSEL(IP6_5_3, TX2, SEL_SCIF2_0),
+       PINMUX_IPSR_MSEL(IP6_7_6, TX2, SEL_SCIF2_0),
        PINMUX_IPSR_MSEL(IP6_7_6, SCIFA2_TXD, SEL_SCIFA2_0),
        PINMUX_IPSR_GPSR(IP6_9_8, IRQ0),
        PINMUX_IPSR_MSEL(IP6_9_8, SCIFB1_RXD_D, SEL_SCIFB1_3),
@@ -5707,7 +5711,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
        },
        { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
                             2, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2, 3) {
-               /* IP2_31_20 [2] */
+               /* IP2_31_30 [2] */
                0, 0, 0, 0,
                /* IP2_29_27 [3] */
                FN_EX_CS3_N, FN_ATADIR0_N, FN_MSIOF2_TXD,
@@ -5727,7 +5731,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                /* IP2_15_13 [3] */
                FN_A24, FN_DREQ2, FN_IO3, FN_TX1, FN_SCIFA1_TXD,
                0, 0, 0,
-               /* IP2_12_0 [3] */
+               /* IP2_12_10 [3] */
                FN_A23, FN_IO2, FN_BPFCLK_B, FN_RX0, FN_SCIFA0_RXD,
                0, 0, 0,
                /* IP2_9_7 [3] */
@@ -5896,7 +5900,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                0, 0,
                /* IP6_2_0 [3] */
                FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B,
-               FN_SCIF_CLK, 0, FN_BPFCLK_E,
+               FN_SCIF_CLK, FN_DVC_MUTE, FN_BPFCLK_E,
                0, 0, }
        },
        { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
@@ -6038,7 +6042,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
                /* IP10_24_22 [3] */
                FN_VI0_R1, FN_VI2_DATA2, FN_GLO_I1_B, FN_TS_SCK0_C, FN_ATAG1_N,
                0, 0, 0,
-               /* IP10_21_29 [3] */
+               /* IP10_21_19 [3] */
                FN_VI0_R0, FN_VI2_DATA1, FN_GLO_I0_B,
                FN_TS_SDATA0_C, FN_ATACS11_N,
                0, 0, 0,