b43: rename b43_wldev's field with ssb_device to sdev

[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / wireless / b43 / b43.h

diff --git a/drivers/net/wireless/b43/b43.h b/drivers/net/wireless/b43/b43.h
index 72821c456b02fcf480525846ffce55e185486c73..fd69d6ae6b882b6ab835cce6e3c165cfe9dc6604 100644 (file)
--- a/drivers/net/wireless/b43/b43.h
+++ b/drivers/net/wireless/b43/b43.h
@@ -153,6 +153,19 @@
 #define B43_BFH_FEM_BT                 0x0040  /* has FEM and switch to share antenna
                                                 * with bluetooth */
 
+/* SPROM boardflags2_lo values */
+#define B43_BFL2_RXBB_INT_REG_DIS      0x0001  /* external RX BB regulator present */
+#define B43_BFL2_APLL_WAR              0x0002  /* alternative A-band PLL settings implemented */
+#define B43_BFL2_TXPWRCTRL_EN          0x0004  /* permits enabling TX Power Control */
+#define B43_BFL2_2X4_DIV               0x0008  /* 2x4 diversity switch */
+#define B43_BFL2_5G_PWRGAIN            0x0010  /* supports 5G band power gain */
+#define B43_BFL2_PCIEWAR_OVR           0x0020  /* overrides ASPM and Clkreq settings */
+#define B43_BFL2_CAESERS_BRD           0x0040  /* is Caesers board (unused) */
+#define B43_BFL2_BTC3WIRE              0x0080  /* used 3-wire bluetooth coexist */
+#define B43_BFL2_SKWRKFEM_BRD          0x0100  /* 4321mcm93 uses Skyworks FEM */
+#define B43_BFL2_SPUR_WAR              0x0200  /* has a workaround for clock-harmonic spurs */
+#define B43_BFL2_GPLL_WAR              0x0400  /* altenative G-band PLL settings implemented */
+
 /* GPIO register offset, in both ChipCommon and PCI core. */
 #define B43_GPIO_CONTROL               0x6c
 
@@ -403,10 +416,10 @@ enum {
 
 /* 802.11 core specific TM State Low (SSB_TMSLOW) flags */
 #define B43_TMSLOW_GMODE               0x20000000      /* G Mode Enable */
-#define B43_TMSLOW_PHYCLKSPEED         0x00C00000      /* PHY clock speed mask (N-PHY only) */
-#define  B43_TMSLOW_PHYCLKSPEED_40MHZ  0x00000000      /* 40 MHz PHY */
-#define  B43_TMSLOW_PHYCLKSPEED_80MHZ  0x00400000      /* 80 MHz PHY */
-#define  B43_TMSLOW_PHYCLKSPEED_160MHZ 0x00800000      /* 160 MHz PHY */
+#define B43_TMSLOW_PHY_BANDWIDTH       0x00C00000      /* PHY band width and clock speed mask (N-PHY only) */
+#define  B43_TMSLOW_PHY_BANDWIDTH_10MHZ        0x00000000      /* 10 MHz bandwidth, 40 MHz PHY */
+#define  B43_TMSLOW_PHY_BANDWIDTH_20MHZ        0x00400000      /* 20 MHz bandwidth, 80 MHz PHY */
+#define  B43_TMSLOW_PHY_BANDWIDTH_40MHZ        0x00800000      /* 40 MHz bandwidth, 160 MHz PHY */
 #define B43_TMSLOW_PLLREFSEL           0x00200000      /* PLL Frequency Reference Select (rev >= 5) */
 #define B43_TMSLOW_MACPHYCLKEN         0x00100000      /* MAC PHY Clock Control Enable (rev >= 5) */
 #define B43_TMSLOW_PHYRESET            0x00080000      /* PHY Reset */
@@ -692,7 +705,7 @@ enum {
 
 /* Data structure for one wireless device (802.11 core) */
 struct b43_wldev {
-       struct ssb_device *dev;
+       struct ssb_device *sdev;
        struct b43_wl *wl;
 
        /* The device initialization status.
@@ -866,22 +879,22 @@ static inline enum ieee80211_band b43_current_band(struct b43_wl *wl)
 
 static inline u16 b43_read16(struct b43_wldev *dev, u16 offset)
 {
-       return ssb_read16(dev->dev, offset);
+       return ssb_read16(dev->sdev, offset);
 }
 
 static inline void b43_write16(struct b43_wldev *dev, u16 offset, u16 value)
 {
-       ssb_write16(dev->dev, offset, value);
+       ssb_write16(dev->sdev, offset, value);
 }
 
 static inline u32 b43_read32(struct b43_wldev *dev, u16 offset)
 {
-       return ssb_read32(dev->dev, offset);
+       return ssb_read32(dev->sdev, offset);
 }
 
 static inline void b43_write32(struct b43_wldev *dev, u16 offset, u32 value)
 {
-       ssb_write32(dev->dev, offset, value);
+       ssb_write32(dev->sdev, offset, value);
 }
 
 static inline bool b43_using_pio_transfers(struct b43_wldev *dev)