[TG3]: Add mailbox read method

[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / net / tg3.h

diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index 0a277c1e75d127fdfdeae270363bae37df73e311..c398b8478d62eae94c2a262fa0213f358c5902e2 100644 (file)
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -2049,6 +2049,11 @@ struct tg3 {
        spinlock_t                      lock;
        spinlock_t                      indirect_lock;
 
+       u32                             (*read32) (struct tg3 *, u32);
+       void                            (*write32) (struct tg3 *, u32, u32);
+       u32                             (*read32_mbox) (struct tg3 *, u32);
+       void                            (*write32_mbox) (struct tg3 *, u32,
+                                                        u32);
        void __iomem                    *regs;
        struct net_device               *dev;
        struct pci_dev                  *pdev;
@@ -2060,6 +2065,8 @@ struct tg3 {
        u32                             msg_enable;
 
        /* begin "tx thread" cacheline section */
+       void                            (*write32_tx_mbox) (struct tg3 *, u32,
+                                                           u32);
        u32                             tx_prod;
        u32                             tx_cons;
        u32                             tx_pending;
@@ -2071,6 +2078,8 @@ struct tg3 {
        dma_addr_t                      tx_desc_mapping;
 
        /* begin "rx thread" cacheline section */
+       void                            (*write32_rx_mbox) (struct tg3 *, u32,
+                                                           u32);
        u32                             rx_rcb_ptr;
        u32                             rx_std_ptr;
        u32                             rx_jumbo_ptr;
@@ -2161,6 +2170,10 @@ struct tg3 {
 #define TG3_FLG2_PROTECTED_NVRAM       0x00100000
 #define TG3_FLG2_USING_MSI             0x00200000
 #define TG3_FLG2_JUMBO_CAPABLE         0x00400000
+#define TG3_FLG2_MII_SERDES            0x00800000
+#define TG3_FLG2_ANY_SERDES            (TG3_FLG2_PHY_SERDES |  \
+                                       TG3_FLG2_MII_SERDES)
+#define TG3_FLG2_PARALLEL_DETECT       0x01000000
 
        u32                             split_mode_max_reqs;
 #define SPLIT_MODE_5704_MAX_REQ                3