import OT_8063_20170412 mali driver

[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / misc / mediatek / gpu / mt8127 / mali / mali / timestamp-arm11-cc / mali_timestamp.h

diff --git a/drivers/misc/mediatek/gpu/mt8127/mali/mali/timestamp-arm11-cc/mali_timestamp.h b/drivers/misc/mediatek/gpu/mt8127/mali/mali/timestamp-arm11-cc/mali_timestamp.h
index 0b53257210aee9fa4432107731afc048afd6a7c5..e6aa3008493562899c90ea5c56e85d408f03302e 100644 (file)
--- a/drivers/misc/mediatek/gpu/mt8127/mali/mali/timestamp-arm11-cc/mali_timestamp.h
+++ b/drivers/misc/mediatek/gpu/mt8127/mali/mali/timestamp-arm11-cc/mali_timestamp.h
@@ -1,7 +1,7 @@
 /*
  * This confidential and proprietary software may be used only as
  * authorised by a licensing agreement from ARM Limited
- * (C) COPYRIGHT 2010-2011, 2013 ARM Limited
+ * (C) COPYRIGHT 2010-2011, 2013-2015 ARM Limited
  * ALL RIGHTS RESERVED
  * The entire notice above must be reproduced on all authorised
  * copies and copies may only be made to the extent permitted
@@ -20,17 +20,17 @@ MALI_STATIC_INLINE _mali_osk_errcode_t _mali_timestamp_reset(void)
         */
 
        u32 mask = (1 << 0) | /* enable all three counters */
-                  (0 << 1) | /* reset both Count Registers to 0x0 */
-                  (1 << 2) | /* reset the Cycle Counter Register to 0x0 */
-                  (0 << 3) | /* 1 = Cycle Counter Register counts every 64th processor clock cycle */
-                  (0 << 4) | /* Count Register 0 interrupt enable */
-                  (0 << 5) | /* Count Register 1 interrupt enable */
-                  (0 << 6) | /* Cycle Counter interrupt enable */
-                  (0 << 8) | /* Count Register 0 overflow flag (clear or write, flag on read) */
-                  (0 << 9) | /* Count Register 1 overflow flag (clear or write, flag on read) */
-                  (1 << 10); /* Cycle Counter Register overflow flag (clear or write, flag on read) */
-
-       __asm__ __volatile__ ("MCR    p15, 0, %0, c15, c12, 0" : : "r" (mask) );
+                  (0 << 1) | /* reset both Count Registers to 0x0 */
+                  (1 << 2) | /* reset the Cycle Counter Register to 0x0 */
+                  (0 << 3) | /* 1 = Cycle Counter Register counts every 64th processor clock cycle */
+                  (0 << 4) | /* Count Register 0 interrupt enable */
+                  (0 << 5) | /* Count Register 1 interrupt enable */
+                  (0 << 6) | /* Cycle Counter interrupt enable */
+                  (0 << 8) | /* Count Register 0 overflow flag (clear or write, flag on read) */
+                  (0 << 9) | /* Count Register 1 overflow flag (clear or write, flag on read) */
+                  (1 << 10); /* Cycle Counter Register overflow flag (clear or write, flag on read) */
+
+       __asm__ __volatile__("MCR    p15, 0, %0, c15, c12, 0" : : "r"(mask));
 
        return _MALI_OSK_ERR_OK;
 }
@@ -40,7 +40,7 @@ MALI_STATIC_INLINE u64 _mali_timestamp_get(void)
        u32 result;
 
        /* this is for the clock cycles */
-       __asm__ __volatile__ ("MRC    p15, 0, %0, c15, c12, 1" : "=r" (result));
+       __asm__ __volatile__("MRC    p15, 0, %0, c15, c12, 1" : "=r"(result));
 
        return (u64)result;
 }