powerpc: Hook in new transactional memory code

[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / powerpc / mm / hash_utils_64.c

diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c
index 3a292be2e07912b903075d6c6bf70ee0e02641d9..1b6e1271719f994e1d16b21621851733658bffa5 100644 (file)
--- a/arch/powerpc/mm/hash_utils_64.c
+++ b/arch/powerpc/mm/hash_utils_64.c
@@ -55,6 +55,7 @@
 #include <asm/code-patching.h>
 #include <asm/fadump.h>
 #include <asm/firmware.h>
+#include <asm/tm.h>
 
 #ifdef DEBUG
 #define DBG(fmt...) udbg_printf(fmt)
@@ -1171,6 +1172,21 @@ void flush_hash_page(unsigned long vpn, real_pte_t pte, int psize, int ssize,
                DBG_LOW(" sub %ld: hash=%lx, hidx=%lx\n", index, slot, hidx);
                ppc_md.hpte_invalidate(slot, vpn, psize, ssize, local);
        } pte_iterate_hashed_end();
+
+#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
+       /* Transactions are not aborted by tlbiel, only tlbie.
+        * Without, syncing a page back to a block device w/ PIO could pick up
+        * transactional data (bad!) so we force an abort here.  Before the
+        * sync the page will be made read-only, which will flush_hash_page.
+        * BIG ISSUE here: if the kernel uses a page from userspace without
+        * unmapping it first, it may see the speculated version.
+        */
+       if (local && cpu_has_feature(CPU_FTR_TM) &&
+           MSR_TM_ACTIVE(current->thread.regs->msr)) {
+               tm_enable();
+               tm_abort(TM_CAUSE_TLBI);
+       }
+#endif
 }
 
 void flush_hash_range(unsigned long number, int local)