MIPS: Octeon: Simplify code by assuming CONFIG_64BIT is always set.

[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / mips / cavium-octeon / octeon-memcpy.S

diff --git a/arch/mips/cavium-octeon/octeon-memcpy.S b/arch/mips/cavium-octeon/octeon-memcpy.S
index 88e0cddca2057addb1ad823844cc3e2351e0c2e7..0ba0eb96d9ac1e3706c613335fd14104ff1c62b5 100644 (file)
--- a/arch/mips/cavium-octeon/octeon-memcpy.S
+++ b/arch/mips/cavium-octeon/octeon-memcpy.S
@@ -79,11 +79,6 @@
 /*
  * Only on the 64-bit kernel we can made use of 64-bit registers.
  */
-#ifdef CONFIG_64BIT
-#define USE_DOUBLE
-#endif
-
-#ifdef USE_DOUBLE
 
 #define LOAD   ld
 #define LOADL  ldl
@@ -119,26 +114,6 @@
 #define t6     $14
 #define t7     $15
 
-#else
-
-#define LOAD   lw
-#define LOADL  lwl
-#define LOADR  lwr
-#define STOREL swl
-#define STORER swr
-#define STORE  sw
-#define ADD    addu
-#define SUB    subu
-#define SRL    srl
-#define SLL    sll
-#define SRA    sra
-#define SLLV   sllv
-#define SRLV   srlv
-#define NBYTES 4
-#define LOG_NBYTES 2
-
-#endif /* USE_DOUBLE */
-
 #ifdef CONFIG_CPU_LITTLE_ENDIAN
 #define LDFIRST LOADR
 #define LDREST  LOADL
@@ -163,6 +138,14 @@
        .set    noreorder
        .set    noat
 
+/*
+ * t7 is used as a flag to note inatomic mode.
+ */
+LEAF(__copy_user_inatomic)
+       b       __copy_user_common
+        li     t7, 1
+       END(__copy_user_inatomic)
+
 /*
  * A combined memcpy/__copy_user
  * __copy_user sets len to 0 for success; else to an upper bound of
@@ -174,6 +157,8 @@ LEAF(memcpy)                                        /* a0=dst a1=src a2=len */
        move    v0, dst                         /* return value */
 __memcpy:
 FEXPORT(__copy_user)
+       li      t7, 0                           /* not inatomic */
+__copy_user_common:
        /*
         * Note: dst & src may be unaligned, len may be 0
         * Temps
@@ -385,12 +370,10 @@ EXC(       sb     t0, N(dst), s_exc_p1)
 
        COPY_BYTE(0)
        COPY_BYTE(1)
-#ifdef USE_DOUBLE
        COPY_BYTE(2)
        COPY_BYTE(3)
        COPY_BYTE(4)
        COPY_BYTE(5)
-#endif
 EXC(   lb      t0, NBYTES-2(src), l_exc)
        SUB     len, len, 1
        jr      ra
@@ -412,7 +395,6 @@ l_exc_copy:
         * Assumes src < THREAD_BUADDR($28)
         */
        LOAD    t0, TI_TASK($28)
-        nop
        LOAD    t0, THREAD_BUADDR(t0)
 1:
 EXC(   lb      t1, 0(src),     l_exc)
@@ -422,10 +404,9 @@ EXC(       lb      t1, 0(src),     l_exc)
         ADD    dst, dst, 1
 l_exc:
        LOAD    t0, TI_TASK($28)
-        nop
        LOAD    t0, THREAD_BUADDR(t0)   # t0 is just past last good address
-        nop
        SUB     len, AT, t0             # len number of uncopied bytes
+       bnez    t7, 2f          /* Skip the zeroing out part if inatomic */
        /*
         * Here's where we rely on src and dst being incremented in tandem,
         *   See (3) above.
@@ -443,7 +424,7 @@ l_exc:
        ADD     dst, dst, 1
        bnez    src, 1b
         SUB    src, src, 1
-       jr      ra
+2:     jr      ra
         nop