Blackfin arch: enable reprogram cclk and sclk for bf518f-ezbrd

[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / blackfin / include / asm / mem_init.h

diff --git a/arch/blackfin/include/asm/mem_init.h b/arch/blackfin/include/asm/mem_init.h
index 3cbc0f81ebf3aa6cb55dadb087e3cb58c0516e55..255a9316ad367e8c5e6b3793007e307033d59d4c 100644 (file)
--- a/arch/blackfin/include/asm/mem_init.h
+++ b/arch/blackfin/include/asm/mem_init.h
@@ -13,7 +13,8 @@
     defined(CONFIG_MEM_GENERIC_BOARD) || \
     defined(CONFIG_MEM_MT48LC32M8A2_75) || \
     defined(CONFIG_MEM_MT48LC8M32B2B5_7) || \
-    defined(CONFIG_MEM_MT48LC32M16A2TG_75)
+    defined(CONFIG_MEM_MT48LC32M16A2TG_75) || \
+    defined(CONFIG_MEM_MT48LC32M8A2_75)
 #if (CONFIG_SCLK_HZ > 119402985)
 #define SDRAM_tRP       TRP_2
 #define SDRAM_tRP_num   2
@@ -100,7 +101,8 @@
     defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \
     defined(CONFIG_MEM_GENERIC_BOARD) || \
     defined(CONFIG_MEM_MT48LC32M16A2TG_75) || \
-    defined(CONFIG_MEM_MT48LC16M16A2TG_75)
+    defined(CONFIG_MEM_MT48LC16M16A2TG_75) || \
+    defined(CONFIG_MEM_MT48LC32M8A2_75)
   /*SDRAM INFORMATION: */
 #define SDRAM_Tref  64         /* Refresh period in milliseconds   */
 #define SDRAM_NRA   8192       /* Number of row addresses in SDRAM */