ARM: entry: data abort: tail-call the main data abort handler

[GitHub/mt8127/android_kernel_alcatel_ttab.git] / arch / arm / mm / abort-ev5tj.S

diff --git a/arch/arm/mm/abort-ev5tj.S b/arch/arm/mm/abort-ev5tj.S
index bce68d601c8be5aa4fb8496ca78e56ddb98a0a46..4006b7a612642b7fa4ec36b5a995ccc9bc1e3a40 100644 (file)
--- a/arch/arm/mm/abort-ev5tj.S
+++ b/arch/arm/mm/abort-ev5tj.S
@@ -4,14 +4,11 @@
 /*
  * Function: v5tj_early_abort
  *
- * Params  : r2 = address of aborted instruction
- *         : r3 = saved SPSR
+ * Params  : r2 = pt_regs
+ *        : r4 = aborted context pc
+ *        : r5 = aborted context psr
  *
- * Returns : r0 = address of abort
- *        : r1 = FSR, bit 11 = write
- *        : r2-r8 = corrupted
- *        : r9 = preserved
- *        : sp = pointer to registers
+ * Returns : r4 - r11, r13 preserved
  *
  * Purpose : obtain information about current aborted instruction.
  * Note: we read user space.  This means we might cause a data
@@ -23,13 +20,11 @@ ENTRY(v5tj_early_abort)
        mrc     p15, 0, r1, c5, c0, 0           @ get FSR
        mrc     p15, 0, r0, c6, c0, 0           @ get FAR
        bic     r1, r1, #1 << 11 | 1 << 10      @ clear bits 11 and 10 of FSR
-       tst     r3, #PSR_J_BIT                  @ Java?
-       movne   pc, lr
-       do_thumb_abort
-       ldreq   r3, [r2]                        @ read aborted ARM instruction
-       do_ldrd_abort
+       tst     r5, #PSR_J_BIT                  @ Java?
+       bne     do_DataAbort
+       do_thumb_abort fsr=r1, pc=r4, psr=r5, tmp=r3
+       ldreq   r3, [r4]                        @ read aborted ARM instruction
+       do_ldrd_abort tmp=ip, insn=r3
        tst     r3, #1 << 20                    @ L = 0 -> write
        orreq   r1, r1, #1 << 11                @ yes.
-       mov     pc, lr
-
-
+       b       do_DataAbort